Technical Field
The present invention generally relates to semiconductor testing, and more particularly to devices and methods for contact resistance measurements in vertical transistor devices.
Description of the Related Art
Precisely measuring source/drain (S/D) contact resistance is a desirable for advancing complementary metal oxide semiconductor (CMOS) technology. Many traditional methods for measuring S/D contact resistance in planar CMOS devices cannot be employed for vertical field effect transistors (VFETs) due to drastic structural differences.